With the advances of semiconductor and computer technology, computer systems are becoming faster and at the same time smaller in size. Desk-top and even lap-top computer systems now possess processing speeds of main-frame computers that used to fill up a small room. Even hand-held computer systems such as personal digital assistants (PDA), which are becoming more popular, are getting more powerful. As computer systems become more miniaturized and inexpensive, more demands are constantly being required of them as well. For instance, they are being asked to perform more time-consuming and complex tasks involving graphics and video processing.
At the same time, as computer systems become more powerful and more miniaturized, power-conservation also presents a difficult challenge to overcome. Because of their small size, hand-held computer systems are powered by battery which have limited operating duration. Since more power is required for faster and more powerful processors, innovative solutions are required to conserve power and thereby extend the battery operating duration.
Within each computer system are many integrated circuits designed to perform different functions such as a memory controller, a hard disk controller, a graphics/video controller, a communications controller, and other peripheral controllers. As is well-known, each of these integrated circuits is supplied a clock signal to be used as a timing reference in synchronizing the operation of the integrated circuit. In general, power consumption increases as a result of the integrated circuit being clocked.
Periodically, an integrated circuit is not needed and is idle insofar as system functionality is concerned. At other times, while a sub-circuit (e.g., combination logic and data path) that performs data processing and transferring in the integrated circuit is still running, other sub-circuits in the integrated circuit are idle. Because these circuits continue to receive a clock signal, their respective internal circuits continue to be exercised and consume significant power, even while they remain idle. Accordingly, to conserve power, the clock signal to idle circuits is disabled through the use of clock gating circuitry.
Referring now to FIG. 1 illustrating a prior-art clock gating implementation. As shown in FIG. 1, integrated circuit 100 consists of two combinational logic circuits 101 and 102 each representing a data processing sub-circuit such as video and graphics circuits. The outputs of combinational logic circuits 101 and 102 are eventually combined into a single data path by combinational logic circuit 103 such as a mixer. The clock gating circuitry of integrated circuit 100 consists of AND-gate 107 and latches 104-106. AND-gate 103 receives as inputs enable signal EN and clock signal CLK. The output of AND-gate 107 is used in triggering latches 104-106. Data from external sources are provided as data inputs to combinational logic circuits 101 and 102. Upon processing their inputs, combinational logic circuits 101 and 102 provide their outputs to latches 104 and 105, respectively. Latches 104 and 105 provide their outputs to combinational logic circuit 103 which combines and processes the input data. Combinational logic circuit 103 provides its output to latch 106. Operationally, enable signal EN combines with AND-gate 103 to enable or disable the entire integrated circuit 100. AND-gate 103 and latches 104-106 combine to act as a gating circuitry for integrated circuit 100.
In such prior-art clock gating technique, the entire integrated circuit must either be enabled or disabled. While such use of clock gating circuitry can be achieved without any great complication, such prior-art method is inflexible and is not the most efficient power management technique since sub-circuits cannot be individually disabled.
Referring now to FIG. 2 illustrating another prior-art clock gating implementation. As shown in FIG. 2, integrated circuit 200 consists of two combinational logic circuits 201 and 202 each representing a data processing sub-circuit such as video and graphics circuits. The outputs of combinational logic circuits 201 and 202 are eventually combined into a single data path by combinational logic circuit 203 such as a mixer. The clock gating circuitry of integrated circuit 200 consists of AND-gates 204-206 and latches 207-209. AND-gates 204-206 receive as inputs enable signals EN1-EN3, respectively, and clock signal CLK. The outputs of AND-gates 204-206 are used in triggering latches 207-209. Data from external sources are provided as data inputs to combinational logic circuits 201 and 202. Upon processing their inputs, combinational logic circuits 201 and 202 provide their outputs to latches 207 and 208, respectively. The outputs of latches 207 and 208 are provided to combinational logic circuit 203 which combines and processes the input data. Combinational logic circuit 203 then provides its output to latch 209. Operationally, enable signals EN1-EN3 combine with AND-gates 204-206 to enable or disable the individual sub-circuits as well as the entire integrated circuit 200. Latches 207-209 and AND-gate 204-206 combine to act as clock gating circuitry for integrated circuit 200.
In this prior-art clock gating technique, clock gating circuitry is implemented for each sub-circuit in the integrated circuit to disable the clock signal to selected sub-circuits or the entire integrated circuit as desired. However, disabling the clock signal to part of an integrated circuit may cause clock skews (i.e., asynchronicity) between two sub-circuits with clock gating circuitry as well as between a sub-circuit with clock gating circuitry and one without. As is well known, clock skews may cause latching of invalid or wrong data. Clock skews may be rectified through the use of delay or inverter circuitry to ensure that sub-circuits with clock gating circuitry and the original clock signal are synchronized. For example, delays 211-212 may be placed at the outputs of AND-gates 204-205, respectively. The delays act to minimize the clock skew problem. In the alternate, inverter 210 may be placed at the output of AND-gate 206. The use of inverter 210 causes the processing time to be reduced by approximately half-clock which introduces a critical path. However, the use of delay or inverter circuitry 210-212 means that additional hardware costs are incurred in the fabrication of integrated circuits. Moreover, the use of delay circuitry such as delay 211-212 may also incur costly delays in the design of integrated circuits because the amount of clock skew is generally not determinable until after place-and-route operations are carried out on the integrated circuit.
Thus, a need exists for a clock gating power management system, apparatus, and method that is efficient and cost-effective.